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W81281 USB Keyboard/ Device Controller
W81281
W81281 Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 11 All Dates 09/01/1997 12/16/1997 7/12/1999 Version 0.50 0.51 0.6 Version on Web First published. Update Features Update registers description Main Contents
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Preliminary
TABLE OF CONTENT
1. 2. 3 4. 5. 5.1 5.2 5.3 GENERAL DESCRIPTION ................................................................................................................1 FEATURES .........................................................................................................................................2 BLOCK DIAGRAM .............................................................................................................................3 PIN CONFIGURATION ......................................................................................................................4 PIN DESCRIPTION ............................................................................................................................6 40 PIN DIP...........................................................................................................................................6 28-PIN SOP .........................................................................................................................................8 48-PIN LQFP......................................................................................................................................9
6 FUNCTIONAL DESCRIPTION ...............................................................................................................11 6.1 FIRST IN FIRST OUT STORAGE (FIFO'S) ORGANIZATION ....................................................................11 6.1.1 INTERFACE TO THE MICROCONTROLLER:.......................................................................11 6.2 REGISTER DESCRITPION ......................................................................................................................12 6.2.1 Status Registers ........................................................................................................................12 6.2.2 Control Registers .......................................................................................................................13 6.3 RESET .................................................................................................................................................15 6.3.1 External Reset (Hardware Reset) ............................................................................................16 6.3.2 Warm Reset (Software Reset) .................................................................................................16 6.4 USB SUSPEND.................................................................................................................................16 6.5 USB RESUME:..................................................................................................................................16 7. 7.1 7.2 7.3 7.4 7.5 8. 9. 10. PROGRAMMING NOTES: ..............................................................................................................17 CONTROL REGISTERS ACCESS:...........................................................................................................17 STATUS REGISTERS ACCESS:..............................................................................................................17 FIFOS ACCESS : .................................................................................................................................17 SET STALL FOR ENDPOINT 0 - 4 : ........................................................................................................17 SET NULL DATA FOR IN TRANSACTION OF EP 0 :................................................................................18 ELECTRICAL CHARACTERISTICS & CAPACITANCE..............................................................19 USB KEYBOARD SAMPLE APPLICATION .................................................................................22 PACKAGE DIMENSIONS................................................................................................................24
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE .................................................28
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W81281
USB Keyboard/ Device Controller
1.
GENERAL DESCRIPTION
W81281 is a low cost, high integration single-chip microcontroller with Universal Serial Bus (USB) interface for keyboard application, it includes the core of Winbond 8-bit microprocessor W78C52 which works on 6MHz. It implements a standard PC keyboard and enables connection to host system through low-speed (1.5Mhz) USB connection . It complies with USB Specification Revision 1.0 and HID Class Definition Revision 1.0. For Keyboard application, W81281 supports an 18 X 8 keyboard scan matrix, which allows suspend wake up, and also provides a port for PS/2 mouse. It consists of an 8051 compatible CPU core, a 6K-byte ROM, a 256-byte SRAM, and three 16-bit programmable timers. W81281 supports one device address and five endpoints, one bi-directional endpoint for Control transfer and four unidirectional endpoints for Interrupt IN transfer. Through modification of firmware of W78C52, it can be used for multifunction device design, such as USB-IR receiver and any Slow-Speed (1.5Mhz) USB peripheral device controller.
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Preliminary
2. FEATURES
Fully compliant with USB spec. Rev.1.0 and HID Class Rev. 1.0 Supporting one device address and five endpoints (one Control transfer, four Interrupt transfer) Implementing USB keyboard with PS/2 mouse connection Microsoft Intellimouse(3D mouse) Supported Supporting 8-bit sense (row) input with wake up interrupt on falling edge, internal pull-ups Supporting 18-bit drive (column) output, open drain with pull-ups 8-bit 8051 compatible CPU core 6K-byte ROM 256-byte SRAM 3 direct drive LED outputs with internal series resisters Supporting warm reset Built-in low voltage reset and EFT/ESD protection circuit Built-in Watch-Dog Timer for device recovery Support Win98 system control function Support suspend/wake-up function, suspend current under 500A Internal 3.3V regulator supported 40-pin DIP, 28-pin SOP and 48-pin LQFP packages 5V CMOS Device
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Preliminary
3
Winbond USB Keyboard/HID Controller
Winbond USB Keyboard/HID Controller (W81281)
RST IDSEL(P30) LED0-2(P33-P35) (x3)
P02SO* . . . (x18) P1SI* (x8)
EFT, LVRST
INT
USB SIE 8052 Micro Processor
XFRI
USB Transceiver
Endpoints Power Down Control Watch Dog Timer 5V to 3.3V Conversion
DD+ VSS VBUS
Clock Generator
*P02SO: P00-P07,P20-P27,SCO16,SCO17 *P1SI:P10-P17
X1
X2
VDD
PSCL PSDA (P32) (P31) External Clock Circuit
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Preliminary
4. PIN CONFIGURATION
VSS D+ DVDD3 SI0/P10 SI1/P11 SI2/P12 SI3/P13 SO04/P04 SO05/P05 SO06/P06 SO07/P07 IDSEL/P30 LED0/P33 PSCLK/P32 PSDA/P31 LED1/P34 LED2/P35 RESET X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SO17 SO16 SO00/P00 SO01/P01 SO02/P02 SO03/P03 SI4/P14 SI5/P15 SI6/P16 SI7/P17 SO015/P27 SO014/P26 SO013/P25 SO012/P24 SO011/P23 SO010/P22 SO09/P21 SO08/P20 VDD X1
40-PIN DIP
VSS VSS D+ DVDD3 AD04 AD05 AD06 AD07 XALE XWR XRD RESET X2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AD00 AD01 AD02 AD03 WK0 WK1 WK2 WK3 NC NC XMODE XINT VDD X1
28-PIN SOP
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SO02/P02 SO03/P03 SO15/P27 SO12/P24 SO11/P23 SO14/P26 SO13/P25 SO10/P22 25 24
SI4/P14
SI5/P15
SI6/P16
36 SO01/P02 SO00/P00 SO16 SO17 EESCL VID1 VID0 EESDA VSS VSS D+ D48 1 37
SI7/P17
NC SO09/P21 SO08/P20 VDD X1
W81281D
X2 RESET LED2/P35 LED1/P34 PSDA/P31 13 12 PSCLK/P32 LED0/P33
NC
VDD3
SI0/P10
SI1/P11
SI2/P12
SO04/P04
SO05/P05
SO06/P06
SO07/P07
SI3/P13
48-pin LQFP
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IDSEL/P30
NC
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Preliminary
5.
5.1
PIN DESCRIPTION
40 PIN DIP
NAME VSS D+ DVDD3 SI0/P10 SI1/P11 SI2/P12 SI3/P13 SO04/P04 SO05/P05 SO06/P06 SO07/P07 IDSEL/P30 LED0/P33 PSCLK/P32 PSDA/P31 LED1/P34 LED2/P35 RESET X2 X1 VDD SO08/P20 SO09/P21 SO10/P22 SO11/P23 SO12/P24 SO13/P25 TYPE POWER I/O I/O POWER I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT OUTPUT INPUT POWER I/O I/O I/O I/O I/O I/O Ground USB signal (+) USB signal (-) DC power 3.3V output Keyboard scan Input 0 / Internal C IO port 1.0 Keyboard scan Input 1 / Internal C IO port 1.1 Keyboard scan Input 2 / Internal C IO port 1.2 Keyboard scan Input 3 / Internal C IO port 1.3 Keyboard scan Output 04 / Internal C IO port 0.4 Keyboard scan Output 05 / Internal C IO port 0.5 Keyboard scan Output 06 / Internal C IO port 0.6 Keyboard scan Output 07 / Internal C IO port 0.7 Vendor ID selection / Internal C IO port 3.0 Num. Lock LED / Internal C IO port 3.3 PS/2 mouse clock pin / Internal C IO port 3.2 PS/2 mouse data pin / Internal C IO port 3.1 Caps Lock LED / Internal C IO port 3.4 Scroll Lock LED / Internal C IO port 3.5 Chip reset pin Clock output Clock input VDD power Keyboard scan Output 08 / Internal C IO port 2.0 Keyboard scan Output 09 / Internal C IO port 2.1 Keyboard scan Output 10 / Internal C IO port 2.2 Keyboard scan Output 11 / Internal C IO port 2.3 Keyboard scan Output 12 / Internal C IO port 2.4 Keyboard scan Output 13 / Internal C IO port 2.5 DESCRIPTION
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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5.1 40-PIN DIP, continued
PIN NO. 29 30 31 32 33 34 35 36 37 38 39 40
NAME SO14/P26 SO15/P27 SI7/P17 SI6/P16 SI5/P15 SI4/P14 SO03/P03 SO02/P02 SO01/P01 SO00/P00 SO16 SO17
TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OUTPUT OUTPUT
DESCRIPTION Keyboard scan Output 14 / Internal C IO port 2.6 Keyboard scan Output 15 / Internal C IO port 2.7 Keyboard scan Input 7 / Internal C IO port 1.7 Keyboard scan Input 6 / Internal C IO port 1.6 Keyboard scan Input 5 / Internal C IO port 1.5 Keyboard scan Input 4 / Internal C IO port 1.4 Keyboard scan Output 03 / Internal C IO port 0.3 Keyboard scan Output 02 / Internal C IO port 0.2 Keyboard scan Output 01 / Internal C IO port 0.1 Keyboard scan Output 00 / Internal C IO port 0.0 Keyboard scan Output 16 Keyboard scan Output 17
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5.2 28-PIN SOP
NAME VSS VSS D+ DVDD3 AD04 AD05 AD06 AD07 XALE XWR XRD RESET X2 X1 VDD XINT XMODE NC NC WK3 WK2 WK1 WK0 AD03 AD02 AD01 AD00 TYPE POWER POWER I/O I/O POWER I/O I/O I/O I/O I/O I/O I/O INPUT OUTPUT INPUT POWER I/O I/O I/O I/O INPUT INPUT INPUT INPUT I/O I/O I/O I/O Ground Ground USB signal (+) USB signal (-) DC power 3.3V output C Interface AD04 (Address/Data 04) C Interface AD05 (Address/Data 05) C Interface AD06 (Address/Data 06) C Interface AD07 (Address/Data 07) C Interface ALE (Address Latch Enable) C Interface WR (Data Write) C Interface RD (Data Read) Chip reset pin Clock output Clock input VDD power C Interface INT (Interrupt) Controller mode setting, it should be kept high Not Used Not Used Wakeup pin, Active low and keep more than 100ns Wakeup pin, Active low and keep more than 100ns Wakeup pin, Active low and keep more than 100ns Wakeup pin, Active low and keep more than 100ns C Interface AD03 (Address/Data 03) C Interface AD02 (Address/Data 02) C Interface AD01 (Address/Data 01) C Interface AD00 (Address/Data 00) DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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5.3 48-PIN LQFP
NAME VDD3 SI0/P10 SI1/P11 SI2/P12 SI3/P13 NC SO04/P04 SO05/P05 SO06/P06 SO07/P07 IDSEL/P30 NC LED0/P33 PSCLK/P32 PSDA/P31 LED1/P34 LED2/P35 RESET X2 X1 VDD SO08/P20 SO09/P21 NC SO10/P22 SO11/P23 SO12/P24 SO13/P25 SO14/P26 SO15/P27 TYPE POWER I/O I/O I/O I/O none I/O I/O I/O I/O I/O none I/O I/O I/O I/O I/O INPUT OUTPUT INPUT POWER I/O I/O none I/O I/O I/O I/O I/O I/O DESCRIPTION DC power 3.3V output Keyboard scan Input 0 / Internal C IO port 1.0 Keyboard scan Input 1 / Internal C IO port 1.1 Keyboard scan Input 2 / Internal C IO port 1.2 Keyboard scan Input 3 / Internal C IO port 1.3 Not Used Keyboard scan Output 04 / Internal C IO port 0.4 Keyboard scan Output 05 / Internal C IO port 0.5 Keyboard scan Output 06 / Internal C IO port 0.6 Keyboard scan Output 07 / Internal C IO port 0.7 Vendor ID selection / Internal C IO port 3.0 Not Used Num. Lock LED / Internal C IO port 3.3 PS/2 mouse clock pin / Internal C IO port 3.2 PS/2 mouse data pin / Internal C IO port 3.1 Caps Lock LED / Internal C IO port 3.4 Scroll Lock LED / Internal C IO port 3.5 Chip reset pin Clock output Clock input VDD power Keyboard scan Output 08 / Internal C IO port 2.0 Keyboard scan Output 09 / Internal C IO port 2.1 Not Used Keyboard scan Output 10 / Internal C IO port 2.2 Keyboard scan Output 11 / Internal C IO port 2.3 Keyboard scan Output 12 / Internal C IO port 2.4 Keyboard scan Output 13 / Internal C IO port 2.5 Keyboard scan Output 14 / Internal C IO port 2.6 Keyboard scan Output 15 / Internal C IO port 2.7 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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5.3 48-PIN LQFP, continued
PIN NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
NAME SI7/P17 SI6/P16 SI5/P15 SI4/P14 SO03/P03 SO02/P02 SO01/P01 SO00/P00 SO16 SO17 EESCL VID1 VID0 EESDA VSS VSS D+ D-
TYPE I/O I/O I/O I/O I/O I/O I/O I/O OUTPUT OUTPUT OUTPUT INPUT INPUT I/O POWER POWER I/O I/O
DESCRIPTION Keyboard scan Input 7 / Internal C IO port 1.7 Keyboard scan Input 6 / Internal C IO port 1.6 Keyboard scan Input 5 / Internal C IO port 1.5 Keyboard scan Input 4 / Internal C IO port 1.4 Keyboard scan Output 03 / Internal C IO port 0.3 Keyboard scan Output 02 / Internal C IO port 0.2 Keyboard scan Output 01 / Internal C IO port 0.1 Keyboard scan Output 00 / Internal C IO port 0.0 Keyboard scan Output 16 Keyboard scan Output 17 Clock pin of External serial EEPROM Vendor ID selection 1 Vendor ID selection 0 Data pin of External serial EEPROM Ground Ground USB signal (+) USB signal (-)
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Preliminary
6
6.1
FUNCTIONAL DESCRIPTION
First In First Out Storage (FIFO'S) Organization
The W81281 has six FIFO's, one for receiving and five for transmitting.
FIFO or SRAM Endpt 0 Receiving Endpt 0 Transmitting Endpt 1 Transmitting Endpt 2 Transmitting Endpt 3 Transmitting Endpt 4 Transmitting
SIZE (Byte ) 8 8 8 8 8 8
NOTES Data received on upstream port which contains the correct address and pids will be stored here for the CPU core to read. The CPU core writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. The CPU core writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. The CPU core writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. The CPU core writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. The CPU core writes the data here which will be sent to the host when the correct address and pids are transmitted by the host.
6.1.1
INTERFACE TO THE MICROCONTROLLER:
The FIFOs communicate with the CPU core by address 06H 0f External DATA Memory Access of CPU during IP.6 = "1".The FIFO access steps are firstly set IP.6 = "1" in CPU core. Secondly, CPU core selects FIFO to access by setting the followed bits in control register 2 : EP0_RD_EN : read "IN" FIFO of Endpoint 0 ( EP0 ). EP0_WR_EN : write "OUT" FIFO of Endpoint 0 ( EP0 ). EP1_WR_EN : write "OUT" FIFO of Endpoint 1 ( EP1 ). EP2_WR_EN : write "OUT" FIFO of Endpoint 2 ( EP2 ). EP3_WR_EN : write "OUT" FIFO of Endpoint 3 ( EP3 ). EP4_WR_EN : write "OUT" FIFO of Endpoint 4 ( EP4 ). Then access FIFO by address 06H of External DATA Memory Access of CPU. For detailed programming steps, refer to section 7.3 Programming Note. 11 Publication Release Date: July 1999 Revision 0.60
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Preliminary
6.2 Register Descritpion
The CPU core accesses registers by External DATA Memory Access during IP.6 = "1"`1'
6.2.1
Status Registers
CPU core can set "High" at USB_EventINT_EN bit of control register 4 to enable interrupt of USB events to INT0. When interrupt comes, CPU reads status register 0 and 1 to check which event occurs. ( refer to section 7.2 for accessing Status Registers ) Status Register 0: Address = 00H (Interrupt Event Flags) BIT 7 6 5 4 3 2 1 0 SYMBOL NAK_EP0_IN ACK_EP0_SETUP ACK_EP0_OUT ACK_EP0_IN ACK_EP1_IN ACK_EP2_IN ACK_EP3_IN ACK_EP4_IN DESCRIPTION NAK occurs from EP0 for IN Transaction. ( only valid during NakEP0In_INT_EN = 1 in Control Register 3 ) ACK occurs from EP0 for SETUP Transaction ACK occurs from EP0 for OUT Transaction ACK occurs from EP0 for IN Transaction ACK occurs from EP1 for IN Transaction ACK occurs from EP2 for IN Transaction ACK occurs from EP3 for IN Transaction ACK occurs from EP4 for IN Transaction
Status Register 1: Address = 01H (Interrupt Event Flags)
BIT 7-6 5 4 3 2 1 0
SYMBOL VID[1:0] Reserved EP0OutNullData Suspend_In USB_Reset Resume_In Reserved
DESCRIPTION Keyboard Scan Matrix Selection. must ignore this value. receiving Null Data at EP0 during OUT Transaction Suspend Mode active ( no traffic on USB Bus > 3 mS ) receiving Reset command from USB Bus receiving Resume command from USB Bus must ignore this value
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Status Register 2: Address = 07H (Data Byte Count of EP0 IN FIFO)
BIT 7-4 3-0 6.2.2
SYMBOL Reserved DataLength_CNT[3:0] Control Registers must ignore those values
DESCRIPTION
Number of Data byte for EP0 FIFO ( receiving Data from USB Bus )
( All registers are set to 00h at power up.)( refer to section 7.1 for accessing Control Registers ) Control Register 0: Address = 02H (Endpoint Enable Control)
BIT 7-5 4 3 2 1 0
SYMBOL Reserved USB_Speed EP1_EN EP2_EN EP3_EN EP4_EN must keep bits = "0" set
DESCRIPTION
igh" for Full Speed; set "Low" for Low Speed
set "High" to enable Endpoint 1 set "High" to enable Endpoint 2 set "High" to enable Endpoint 3 set "High" to enable Endpoint 4
Control Register 1: Address = 03H (Device Address Setting)
BIT 7 6-0
SYMBOL Bus_Connection Device_Address[6:0]
DESCRIPTION connect up stream port on USB Bus after chip initialization done Setup Device Address
Control Register 2: Address = 04H (FIFO Access Control)
BIT 7 6
SYMBOL Reserved Set_Stall must keep bit = "0".
DESCRIPTION
Set Stall for EP 0 -4 ( refer to section 7.4 for programming )
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5 4 3 2 1 0 EP0_RD_EN EP0_WR_EN EP1_WR_EN EP2_WR_EN EP3_WR_EN EP4_WR_EN Set "High" before reading IN FIFO of EP0 (receiving Data from USB Bus ) Set "High" before writting OUT FIFO of EP0 (transmitting Data to USB Bus ) Set "High" before writting OUT FIFO of EP1 (transmitting Data to USB Bus ) Set "High" before writting OUT FIFO of EP2 (transmitting Data to USB Bus ) Set "High" before writting OUT FIFO of EP3 (transmitting Data to USB Bus ) Set "High" before writting OUT FIFO of EP4 (transmitting Data to USB Bus )
Control Register 3: Address = 05H (USB Event Control)
BIT 7 6 5 4 3 2 1 0
SYMBOL Reserved NakEP0In_INT_EN Set_EP0NullData Warm_Reset Resume_Out Set_Suspend Read_Event Set_EP0_Nak must keep bit = "0"
DESCRIPTION
Enable interrupt event when NAK comes from EP0 for IN Transaction set Null Data for IN Transaction of EP 0 ( refer to section 7.5 for programming ) Active Warm Reset Send Resume command (K-state) to USB Bus ( Set_Suspend should be "1" ) Set suspend mode active Set "High" during reading Status Registers ( refer to section 7.2 for programming ) Set "High" for responsing Nak when IN/OUT Transaction of EP0 come
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Control Register 4: Address = 08H (Interrupt Enable Control)
BIT 7-4 3 2 1 0
SYMBOL Reserved Remote_Wakeup_EN USB_EventINT_EN SCANOUT[17] SCANOUT[16] must keep bits = "0"
DESCRIPTION
for Remote Wakeup Enable from Keystroke or Mouse moving for USB event interrupt enable output port value of port SO17 output port value of port SO16
Control Register 5: Address = 09H (CPU Reset Control)
BIT 7-2 1 0
SYMBOL Reserved UC_WarmReset_EN DisconUSB_Bus_Disable must keep bit = "0"
DESCRIPTION
set "High" for reseting CPU when Warm_Reset = "1" set "High" keeping device conecting with USB Bus during software or hardware reset set ow" disconnecting with USB Bus during software or hardware reset
Control Register 6: Address = 0EH (Watch Dog Timer Reset)
BIT 7-0
SYMBOL Reset_WDT
DESCRIPTION Clear WDT = 00H when set Reset_WDT = AAH
6.3
Reset
The W81281 supports three types of reset. During a reset, all registers of the CPU core and USB return to their default status, and USB device address is set to zero.
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6.3.1 External Reset (Hardware Reset) As in 8051 series controller, the external RESET signal is sampled at S5P2. To take effect, it must be held high at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line. The reset logic also has a special glitch remocal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON(with exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. 6.3.2 Warm Reset (Software Reset)
W81281 provides a warm reset by setting "High" at Warm_Reset bit of control register 3. The W81281 handles the USB reset function independently from the CPU core. If a Single Ended Zero (SE0) is detected on the upstream port for greater then 2.5us, then the interrupt is enabled. The CPU core read flag from USB_Reset bit of status register 1 then CPU - to reset the device address to 0, and enter the default state. No any reset timing occurs. or - to set "High" at Warm_Reset bit of control register 6.3.3 WDT Reset (Hardware Reset) There is a Watch Dog Timer installed in W81C281. CPU should periodically clear WDT to 00H by setting Reset_WDT=AAH before WDT time out. If CPU hangs WDT will time-out and cause hardware reset.
6.4
USB SUSPEND
If there is no upstream activity for 3 msec then the Suspend_In flag is set and the interrupt enabled. When Suspend_In flag is read, CPU core actives power down mode for W81281 go into suspend
6.5
USB RESUME:
The suspend state can be exit by a 'resume'. The resume can occur by three methods. * The host can send a resume to all ports by placing a 0 (K state) on the bus. The W81281 sees the resume, , and enables the interrupt. In this case, the CPU core does not have to perform any functions. * The host can reset the bus. * When any falling edge is detected on CPU port1(keystrokes). The CPU core will exit from power down mode and initiate a resume by setting Resume_Out in the Control Register 3 which will cause a K state to be sent. To un-resume, the CPU core must clear the Resume_Out bit in the Control Register 3.
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7. PROGRAMMING NOTES:
The W81281 uses reserved bit of the Interrupt Priority Register IP.6 as a pre-decoding bit to implement a alternative register and FIFO by External Data Memory Access of CPU core. Programming functions described as below:
7.1
Control Registers Access:
Step 1: set IP.6 = 1 Step 2: access Control Register (by MOVX Instruction) Step 3: set IP.6 = 0
7.2
Status Registers Access:
Step 1: set IP.6 = 1 Step 2 : set Read_Event = 1 in Control Register 3 ( by MOVX Instruction ) step 3 : access Status Registers ( by MOVX Instruction ) step 4 : set IP.6 = 0
7.3
FIFOs Access :
step 1 : set IP.6 = 1 step 2 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction ) step 3 : access FIFO by address 06H of MOVX Instruction step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction ) step 5 : set IP.6 = 0
7.4
Set Stall for Endpoint 0 - 4 :
step 1 : set IP.6 = 1 step 2 : set Set_Stall = 1 (by MOVX Instruction ) step 3 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction ) step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction ) step 5 : set Set_Stall = 0 (by MOVX Instruction ) step 6 : set IP.6 = 0
Note : 1. EP0_RD_EN = 1 for OUT Transaction of
EP0. 17 Publication Release Date: July 1999 Revision 0.60
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2. EP0_WR_EN = 1 for IN Transaction of EP0.
7.5
Set Null Data for IN Transaction of EP 0 :
step 1 : set IP.6 = 1 step 2 : set Set_EP0NullData = 1 (by MOVX Instruction ) step 3 : set EP0_WR_EN = 1 (by MOVX Instruction ) step 4 : set EP0_WR_EN = 0 (by MOVX Instruction ) step 5 : set Set_EP0NullData = 0 (by MOVX Instruction ) step 6 : set IP.6 = 0
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8. ELECTRICAL CHARACTERISTICS & CAPACITANCE
J (Ta = 0 to + 70 ,JVDD = +5V 5% ) SYMBOL VDD VIL VIL1 VIH1 VIH2 VOH VOL IOFL IIH DESCRIPTION Power Support Input Low Voltage (except RESET) Input Low Voltage (RESET) Input High Voltage (except RESET) Input High Voltage (RESET) Output High Voltage (except D+/D-) Output Low Voltage (except D+/D-) Output Leakage Current (High-Z state) Input Leakage Current 0.4 -10 -10 10 10 2.0 3.5 2.4 MIN. 4.0 TYP. 5.0 MAX. 5.5 0.8 0.6 UNIT V V V V V V V uA uA VDD=5.5V VIN=VDD IIL Input Leakage Current -10 10 uA VDD=5.5V VIN=VSS IOH=-4mA IOL= 4mA NOTE
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Symbol D+/D- Leakage Current: Hi-Z State Data Line Leakage D+/D- Input Levels: Differential Input Sensitivity Differential Common Mode Range Single Endge Receiver Threshold D+/D- Output Levels: Static Output Low Static Output High D+/D- Capacitance: Transceiver Capacitance D+/D- Driver Characteristics: Transition Time: Rise Time Fall Time Rise / Fall Time Matching Output Signal Crossover Voltage D+/D- Data Source Timings: Low Speed Data Rate Source Differential Driver Jitter To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew D+/D- Data Receiver Timings: Receiver Data Jitter Tolerance To Next Transition For Paired Transitions Receiver SE0 Tolerance during Differential Transition TDJR1 TDJR2 TLST -75 -45 75 45 210 ns ns ns TDJ1 TDJ2 TEOPT TDEOP -95 -150 1.25 -40 95 150 1.50 100 ns ns s ns TDRATE Ave.Bit Rate (1.5Mb/s 1.5%) 1.4775 1.5225 Mbs TR TF TRFM VCRS CL=50pF/350pF CL=50pF/350pF (TR / TF) 75 75 80 1.3 300 300 125 2.0 ns ns % V CIN Pin to GND 20 pF VOL VOH RL of 1.5k to 3.6V RL of 1.5k to GND 2.8 0.3 3.6 V V VDI VCM VSE (D+)-(D-) Includes VDI range 0.2 0.8 0.8 2.5 2.0 V V V ILO 0 V < VIN < 3.3V -10 +10 A Conditions Min Max Unit
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EOP Width at receiver Must reject as EOP Must accept as EOP TEORP1 TEOPR2 330 675 ns ns
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W81281
Preliminary
9. USB KEYBOARD SAMPLE APPLICATION
1. For 40 pin DIP package
W81281 USB Keyboard Reference Sh i
U1 VCC R6 R7 R1 7.5K VCC USB1 USB-CONN 1 2 3 4 65 L7 L8 L1 L2 FB FB FB FB C4 0.1u 30 30 ScanIn0 ScanIn1 ScanIn2 ScanIn3 ScanIn4 ScanIn5 ScanIn6 ScanIn7 ScanOut0 ScanOut1 ScanOut2 ScanOut3 ScanOut4 ScanOut5 ScanOut6 ScanOut7 ScanOut8 ScanOut9 ScanOut10 ScanOut11 ScanOut12 ScanOut13 ScanOut14 ScanOut15 ScanOut16 ScanOut17 VCC W81281 L3 FB PSDA L4 FB PSCLK L5 FB L6 FB JP4 1 2 3 4 5 6 PS/2 MOUSE 5 6 7 8 34 33 32 31 38 37 36 35 9 10 11 12 23 24 25 26 27 28 29 30 39 40 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 VDD VDD3 VSS RESET X1 X2 IDSEL LED0 LED1 LED2 DD+ PSDA PSCLK 22 4 1 19 21 20 13 14 17 18 3 2 16 15
VCC
+
C6 10u
UU+
RESET X1 X2 IDSEL LED0 LED1 LED2
+
C5 10u
DD+ PSDA PSCLK
VCC
CapsLoc NumLoc k
R 100ohm be an short while not used J
ScrollLoc
D1 D2 D3
C7 47p
C1 47p
R2 100
R3 100
R4 100
LED0 LED1 VCC LED2 + C8 10u RESET R5 3.3K C2 X1 JP1 30p C3 X2 30p IDSEL X1 6MHZ Crystal / Resonator JUMPER JUMPER JP2 JUMPER Only one Jumper can be short or all JP3
22 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
For 48 pin LQFP package reference circuit
W81281 (48pin LQFP) USB Keyboard Reference Schematic
VCC
CapsLock
L3 VCC
FB
VCC
NumLock
D1
D2
D3
ScrollLock
R 100ohm can be short while Jumper not used R2 R3 R4
U1 ScanIn0 ScanIn1 ScanIn2 ScanIn3 ScanIn4 ScanIn5 ScanIn6 ScanIn7 ScanOut0 ScanOut1 ScanOut2 ScanOut3 ScanOut4 ScanOut5 ScanOut6 ScanOut7 ScanOut8 ScanOut9 ScanOut10 ScanOut11 ScanOut12 ScanOut13 ScanOut14 ScanOut15 ScanOut16 ScanOut17 2 3 4 5 34 33 32 31 38 37 36 35 7 8 9 10 22 23 25 26 27 28 29 30 39 40
PSDA
+ C6
L4
JP4
SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17
VDD 1 VDD3 45 VSS 46 VSS RESET
18 20 11
21
10u
PSCLK RESET X1 X2 IDSEL VID0 VID1 LED0 LED1 LED2
Option DD+
L5
FB
L6
FB
C7
FB
C1
1 2 3 4 5 6
100
100
100
PS/2 MOUSE 47p 47p
LED0 LED1 LED2
X1 19 X2 IDSEL 43 VID0 42 VID1 LED0 16 LED1 17 LED2 D- 47 D+ PSCLK 15 PSDA 41 EESCL 44 EESDA NC 12 NC 24 NC
6 14 48 13
JP1 VCC
JP2
JP3
PSCLK PSDA EESCL EESDA
EESDA EESCL
U2 5 6 7 8
JUMPER JUMPER JUMPER
VSS 3 A2 2 A1 1 A0 IDSEL
4 Only one Jumper can be short or all open
SDA SCL RC VCC
24LC04B
W81C281-48
VID0
VCC
JP4
JUMPER
VID1
R6 R7 R1 JP5
30 30
UU+
VCC
JUMPER
7.5K
USB1 VCC L7 L8 L1 L2 C2 + C8
USB-CONN
1 2 3 4 5 6
FB FB
+ C5
X1 RESET
10u 30p
C3 R5 X1
6M
X2
Title
FB FB
C4
0.1u
10u
inbond
WINBOND ELECTRONICS CORP.
W81281 USB Keyboard Reference Schematic Size B Date: Document Number 281DEMO4.SCH Monday, January 25, 1999 Sheet 1 of 1 Rev 1.3
3.3K
30p
23 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
10. PACKAGE DIMENSIONS
40-pin DIP
Symbol
Dimension in inches
Dimension in mm
Min.
0.010 0.150 0.016 0.048 0.008
Nom. Max.
0.210
Min. Nom. Max.
5.33 0.25
D 40 21
A A1 A2 B B1 c D E E1 e1 L
a
0.155 0.018 0.050 0.010 2.055
0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15
3.81 0.41 1.22 0.20
3.94 0.46 1.27 0.25 52.20
4.06 0.56 1.37 0.36 52.58 15.49 13.97 2.79 3.56 15
0.590 0.540 0.090 0.120 0 0.630
0.600 0.545 0.100 0.130
14.99 13.72 2.29 3.05 0 16.00
15.24 13.84 2.54 3.30
E1
eA S
1 S 20 E c A A2 L B B1 e1 A1 Base Plane Seating Plane eA
0.650
0.670 0.090
16.51
17.02 2.29
Notes:
1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
a
28-pin SOP
28
15
c
Control demensions are in milme
DIMENSION IN MM SYMBOL MIN. A E H
E
DIMENSION IN INCH MAX. 2.65 0.30 0.51 0.32 7.60 18.10 MIN. 0.093 0.004 0.013 0.009 0.291 0.697 0.050 BSC 10.65 0.10 0.394 0.419 0.004 0.016 0 0.050 8 MAX. 0.104 0.012 0.020 0.013 0.299 0.713
2.35 0.10 0.33 0.23 7.40 17.70 1.27 BSC 10.00
E
A1 b c E
L
D
1
D
14
0.25 O
e H Y A L
0.40 0
1.27 8
Y SEATING PLANE b e A1 GAUGE PLANE
24 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
48-pin LQFP
HD D
36 25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
25 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
26 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
27 Publication Release Date: July 1999 Revision 0.60
W81281 USB Keyboard Reference h i
U1 VCC R6 R7 R1 7.5K VCC USB1 USB-CONN 1 2 3 4 65 L7 L8 L1 L2 FB FB FB FB C4 0.1u 30 30 ScanIn0 ScanIn1 ScanIn2 ScanIn3 ScanIn4 ScanIn5 ScanIn6 ScanIn7 ScanOut0 ScanOut1 ScanOut2 ScanOut3 ScanOut4 ScanOut5 ScanOut6 ScanOut7 5 6 7 8 34 33 32 31 38 37 36 35 9 10 11 12 23 24 25 26 27 28 29 30 39 40 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 W81281 VDD VDD3 VSS RESET X1 X2 IDSEL LED0 LED1 LED2 DD+ 22 4 1 19 21 20 13 14 17 18 3 2 NumLock
W81281
VCC
Preliminary
+ C6 10u RESET X1 X2 IDSEL LED0 LED1 LED2
VCC
UU+
W81281 (48pin LQFP) USB Keyboard Reference Schematic
+ C5 10u
CapsLock
DD1 D2D+ D3
VCC
U1 ScanIn0 ScanIn1 ScanIn2 ScanIn3 ScanIn4 ScanIn5 ScanIn6 ScanIn7 ScanOut0 ScanOut1 ScanOut2 ScanOut3 ScanOut4 ScanOut5 ScanOut6 ScanOut7 ScanOut8 ScanOut9 ScanOut10 ScanOut11 ScanOut12 ScanOut13 ScanOut14 ScanOut15 ScanOut16 ScanOut17 2 3 4 5 34 33 32 31
PSDA
+ C6
L4
ScanOut8 L3 VCC ScanOut9 FB ScanOut10 ScanOut11 ScanOut12 ScanOut13 ScanOut14 ScanOut15
ScrollLock
16 PSDA 15 PSCLK R 100ohm can
be short while Jumper not used R2 R3 R4
PSDA PSCLK
JP4
SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7
VDD 1 VDD3 45 VSS 46 VSS RESET
18 20 11
21
10u
VCC RESET X1 X2 IDSEL VID0 VID1 LED0 LED1 LED2
DD+
PSCLK
L5
FB FB
ScanOut16 ScanOut17
L6
FB
C7 C1
1 2 3 4 5 6
100
100
100
PS/2 MOUSE
L3 FB JP4 1 2 3 4 5 6 L6 FB
PSCLK SO7
22 23 25 26 27 28 29 30 39 40
38 37 SO0 36 SO1 PSDASO2 35 7 SO3 8 SO4 9 SO5 10 SO6
X1 19 X2 L4 IDSEL 43 VID0 42 VID1 LED0 16 FB LED1 17 LED2 D- 47 D+ FB PSCLK 15 PSDA 41 EESCL 44 C7 EESDA 47p6 NC 12 NC 24 NC
14 48 13
47p
47p
LED0
VCC
CapsLoc LED1 NumLoc
D1 LED2 D2
ScrollLoc
D3
JP1 JP2 JP3
L5
Option
SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17
PSCLK PSDA EESCL EESDA C1 47p
PS/2 MOUSE EESDA EESCL
U2 5 6 7 8
SDA SCL RC VCC
R 100ohm be an short 4 VSS 3 while Jumper A2 2 not used A1 1 A0
VCC
JUMPER JUMPER JUMPER
R2 100 R3 100 IDSEL R4 100
Only one Jumper can be short or all open
24LC04B
LED0 LED1
W81C281-48
VCC LED2 + C8 10u
VCC R6 R7 R1
VID0
JP4
C2 X1
JUMPER
U-
RESET
30 30
JP1 X1 6MHZ Crystal / Resonator X2
+ C8 VCC
JP2 JUMPER
VID1 JP3
JP5
30p U+ C3
VCC
JUMPER
JUMPER
C2
7.5K
USB1
JUMPER
R5 3.3K
L7 L8 L1 L2
USB-CONN
1 2 3 4 5 6
FB FB
X1 RESET IDSEL
30p
+ C5
10u 30p
C3 R5 X1
6M
X2
Title
Only one Jumper can be short or all open
FB FB
C4
0.1u
10u
inbond
WINBOND ELECTRONICS CORP.
W81281 USB Keyboard Reference Schematic Size B Date: Document Number 281DEMO4.SCH Monday, January 25, 1999 Sheet 1 of 1 Rev 1.3
3.3K
30p
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE
VID: 0000 PID: 0801(with PS/2 mouse) PID: 0802(without PS/2 mouse) 101(AT)/102(Europe+Macro)(+Fn)/103(Korean)(Brazillian)/106(Japan.)+Windows 95 keys compatible
28 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
SI0
\ J-NCHG
SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 24 14 12 07 34 05 39 3F 60 5A E1 EC 8B F5 FA EB 31 64 7 Q O D B Caps F6 P_8 P_2 " K45 K29 K131 Shift-L 13 P 87 89
K14
J-14
Macro
SI1
K56
J-56
29 ESC 2F [ 30 ] 32
K42
\
25 8 0A G 0B H 36 < 37 > 38 ? 4C Del 55 * 3E F5 5F P_7 3D F4 47 57 Scroll P_+ 45 F12 3C F3 53 5E Num P_6 44 F11 50 Left 4F Right 49 Ins 3B F2 43 F10 5D 58 48 Power P_5 P_Entr Pause 3A F1 42 F9 5C P_4 63 P_. 4B E4 PgUp Ctrl-R 0D J 0E K 0F L 33 ; 19 V 06 C 1B X 1D Z 4D End 10 M 4E PgDn 41 F8 56 P_62 P_0 52 Up E0 Ctrl-L
1A W
09 F
35 ~
11 N
2C SPC
40 F7
61 P_9
5B P_3
4A Wake E3 Home -up Win-L
F9
91
K150
Kor0-L
EE EA
SI2
1E 1
26 9
08 E
F1
01
01
SI3
1F 2 28 Enter 51 Down 04 A 16 S
27 0
15 R
F0 EF
Sleep
01
01
F8
E5 Shift-R
90
K151
Kor1-R
SI4
20 3
2D -
17 T
F4 F3
E2 Alt-L
87
K56
BZ0
E5 Shift-R
SI5
21 4
2E +
1C Y
E9 E8
54 /
F7 ED
8A
K132
J-CHG
94
K107
BZ1
SI6
22 5
2A BKS
18 U
F2
65 APP
E6 E7 Alt-R Win-R 88
K133
J-ROMA
FF F6 FB
SI7
23 6
2B TAB
0C I
59 46 P_1 PrtScr
29 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
NOTE 1: The contents in the table are hexadecimal HID codes and function descriptor. 2: Six are scan-in lines, Sox are scan-out lines. 3: The three ACPI power management keys for Windows 98 are Power (SI4-SO12), Sleep (SI5SO13) and Wakeup (SI1-SO12).
Multimedia Buttons & Reserved Buttons (W81281-004)
HID Code E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Functions (ref. Qtronix) Play/Pause Stop/Eject Rewind Forward Record Volume+ VolumeMute WWW Previous Next Stop Search ScrollUp ScrollDown Menu Suspend Coffee Xfer Calculator Reserved (OnNow -Power) Reserved (OnNow -Sleep) Reserved (OnNow -Wakeup) Reserved
30
Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
HID Codes vs. Legacy Scan-Codes (W81281-004)
SI0
50 72 72 2B 5D 5C 2A 12 12 7B 67 85
SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 24 E1 14 12 07 34 05 39 3F 60 5A 64 EC 8B F5 FA EB 31 K8 K17 K25 K33 K41 K50 K30 K117 K96 K98 K44 K45 K29 K131 13 K26 87
K56
73 51 51 47 6C 6E 63 5E 5B 1F 8B
56 61 13 08 3D 3D 10 15 15 18 44 44 20 23 23 28 52 52 30 32 32 3A 58 14 40 0B 2F 48 75 75
SI1
29 K110 09 K34 0A K35
52 70 70 48 75 63 1D 14 11
25 K9 2F K27 30 K28 32
K42
53 71 71 49 7D 6F 1D 14 58
1A K18 4D K81 36 3A 42 5C K53 K112 K120 K92 63 K104 58 K108
FF FF 62
35 K1 10 K52 4B K85 48 K126
5E 37
11 K51 4E 41 56 K86 K119 K105 E4 K64 62 K99 52 K83 E0 K58
2C 40 61 5B K61 K118 K101 K103 4A K80
E3 K127
89
K14
7D 6A 5D
F9
01 91
K150
F1 F1 F1
EE EA
01 76 08 09 3E 3E 11 1D 1D 19 4D 4D 21 2B 2B 29 0E 0E 31 31 31 39 29 29 41 83 37 49 7D 7D 51 7A 7A
SI2
1E K2 0B K36 0D K37 0E K38
57 78 56
26 K10
08 K19
F1 F0 EF
01
02 16 16 0A 46 46 12 24 24 1A 54 54 22 34 34 4F 69 65 32 3A 3A 51 7A 6D 42 0A 3F 4A 7B 84
SI3
1F K3 28 K43 51 K84 04 K31
1E 1C 1C
27 K11 1D K46 1B K47 06 K48 19 55 3E 5F K49 K100 K116 K91 59 K93 4C 3D 47 57 45 K76 K115 K125 K106 K123
58 07 5E
15 K20 37 3B 43 5D K54 K113 K121 K97 38 3C 53 5E 44 K55 K114 K90 K102 K122 50 K79
4B 6B 61
01
01
F8
E5 K57
36 59 59
90
K151
F0 F2 F2
03 1E 1E 0B 45 45 13 2D 2D 1B 5B 5B 23 33 33 2B 5D 53 33 41 41 3B 05 07 43 01 47 4B 6B 6B
SI4
20 K4
2D K12
17 K21
F4 E9
5F 3F
87
K56
73 51 51
E5 K57
36 59 59
04 26 26 0C 4E 4E 14 2C 2C 1C 5A 5A 24 3B 3B 2C 1A 1A 34 49 49 3C 06 0F 44 09 4F 4C 73 73 1C 5A 79
SI5
21 K5 0F K39 33 K40
2E K13
1C K22
F3
4F K89
4D 74 6A
E2 K60
38 11 19
F7 E8 ED F2
E6 K62
38 11 39
94
K107
7E 6D 7B
05 25 25 0D 55 55 15 35 35 50 72 60 25 42 42 2D 22 22 35 4A 4A 3D 04 17 45 77 76 4D 74 74
SI6
22 K6 16 K32
2A K15
18 K23
E7 K128
5C 27 8C
FF
06 2E 2E 0E 66 66 16 3C 3C
26 4B 4B 2E 21 21 53 71 64 3E 0C 1F 46 7E 5F 4E 79 7C
SI7
23 K7
2B K16
0C K24
46 K124
37 7C 57
49 K75
52 70 67
54 K95
35 4A 77
8A
K132
79 64 86
65 K129
5D 2F 8D
88
K133
70 13 87
F6
FB
07 36 36
0F 0D 0D
17 43 43 1F 1B 1B 27 4C 4C 2F 2A 2A 37 7C 7E 3F 03 27 47 6C 6C 4F 69 69
31
Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
NOTE: The contents in the table are hexadecimal HID Code + Order Number of Legacy Keys + Legacy Scan-Code (set1 set2 set3).
32 Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
Winbond USB Product Roadmap
HUB W81C180 180 4 pot HUB RB5387 W81181D 4 pot HUB
W81182 Legacy HUB
W81C280 USB K/B
K/B
W81281 USB 8052
W81282 HUB+K/B
~
Winbond USB Product Brief
* W81C180: USB 4 Port Hub Controller * W81181D: High Integrated USB 4 Port Hub Controller * W81182:USB Legacy Hub, Translate EPP, Serial, PS/2 to USB Connection, Including 4 port USB Hub * W81C280: USB K/B Controller * W81281: High Integrated USB+8052 Controller or USB K/B Controller * W81282:USB 4 Port Hub + K/B Controller
~
2H/98 1Q/99
2Q/99
3Q/99
4Q/99
1Q/2K
33
Publication Release Date: July 1999 Revision 0.60
W81281
Preliminary
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
34 Publication Release Date: July 1999 Revision 0.60
This datasheet has been download from: www..com Datasheets for electronics components.

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